This invention relates to integrated circuits and more specifically to testing of integrated circuits, and especially to timing calibration of integrated circuit testing apparatus.
High speed digital buses for fast memories, processors and various chip sets, all of which are integrated circuits, often have critical timing skew requirements for signals at their input and output terminals (xe2x80x9cpinsxe2x80x9d). Such integrated circuits typically have input/output data rates of, e.g., one Gigabit per second and higher. This has led to much tighter test accuracy requirements than previously known. All possible calibration (timing) errors must be addressed in order to obtain tester apparatus timing accuracy to the level required to measure the set-up, hold and propagation delay times required by these high data rate devices. Typical calibration requirements are 50 picosecond to 100 picosecond timing accuracy.
It is well known that various factors impede such accuracy. These include trace (conductor) lengths on the device interface board. The device interface board is part of the assembly which interfaces between the actual integrated circuits being tested and the electronic portions of the test apparatus (e.g., ATExe2x80x94automatic test equipment). Examples of the pertinent types of test apparatus (testers) are ITS9000KX, RDX2200, and RDX2400, all supplied by Schlumberger Technologies, Inc. On these device interface boards the trace links may change slightly during the fabrication process or if cables are used instead of traces, the cables may not match the design length due to fabrication tolerances. Additionally, dielectric constants of the insulation material used in the printed circuit board, which is the material of the device interface board, or in the cables, may vary. Additionally, the dielectrics have a loss factor which is not predictable and typically differs in response to changes in frequencies of the signals being propagated. A number of other fabrication factors also come into play, such as AC impedance changes due to the traces or cables, solder vias creating impedance discontinuities, electrical interconnections pads providing impedance discontinuities, and cable terminations affecting impedances.
Resulting technical problems are frequency dependent alternating current (AC) loss, reflections in variations and propagation delay, all of which complicate calibration of the device interface board and hence tend to reduce test accuracy.
Attempts to measure these timing errors traditionally include manual oscilloscope measurements to perform a check of accuracy and skew in timing. Automated probe measurements are an automated version of the manual oscilloscope approach. Also, TDR (time domain reflection) is a technique for measuring propagation delays in a transmission line. This is accomplished in the context of device interface boards by transmitting a signal down a transmission line with a source terminated driver and observing the actual voltage level at the transmission line in the transmission line side of the driver source impedance. This is possible due to the discontinuity at the device under test (DUT) due to the integrated circuit socket which is in the signal path from the tester apparatus through the device interface board. There are also other discontinuities present which affect the accuracy.
See also copending and commonly owned U.S. patent application Ser. No. 09/514,708, entitled xe2x80x9cMethod And Apparatus For Socket Calibrationxe2x80x9d commonly invented and incorporated herein by reference in its entirety, filed Feb. 28, 2000, which describes calibration for testing using a set of reference blocks that serve to switch a common probe tester channel to individual channels in succession in the pins of the integrated circuit device under test. That application is incorporated herein by reference in its entirety. Each reference block is effectively a xe2x80x9cdummyxe2x80x9d integrated circuit which contains traces shorted between certain of its pins (terminals). As each reference block is inserted into the device under test socket in the tester apparatus, that reference block switches the signal path to a new pin. Each reference block trace is short and all blocks in the set have identical trace lengths. The reference blocks are typically fabricated to have the same external features and dimensions as the actual integrated circuit DUT so they may be cycled through the tester apparatus socket using the conventional automated device handler.
The number of reference blocks required is equal to the number of DUT socket signal terminals being subject to timing calibration for a particular device under test. Each trace connects a different signal terminal to a common reference terminal on each reference block in the set. To perform the timing calibration, the reference blocks may be mounted on a single fixture one at a time using multi-site fixtures, or multiple reference blocks may be used in parallel. The fixture provides electrical connection of the reference block to the conventional load board of the tester apparatus and ultimately the electronic portions of the tester apparatus.
The tester apparatus then programs a signal pulse on the signal terminal of the reference block, and measures the amount of time that elapses until the resulting pulse occurs on the reference terminal of the reference block. Polarity is then reversed using the programmable I/O feature of the tester apparatus and the tester apparatus programs a signal pulse on the reference terminal of the reference block. (That is, the direction of signal flow is reversed.) The tester apparatus then measures the amount of time that elapses until the resulting signal pulse occurs on the signal terminal of the reference block. These relative timing offset values are saved in the tester apparatus memory. These steps are repeated for each reference block in the set. The highest relative offset timing values obtained are used to calibrate the tester timing for both programming a signal pulse on the signal terminals (known as xe2x80x9cdrivingxe2x80x9d) and measuring a signal pulse on the signal terminals (known as xe2x80x9ccomparingxe2x80x9d). A final calibration step is performed to equalize the difference between the difference between the relative timing offset for programming a signal pulse on the reference terminal and for measuring a signal pulse on the reference terminal. The final calibration step can be performed in several different ways.
The above described reference block method and apparatus are extended here. For high speed integrated circuits there are situations where the number of reference blocks for tester calibration may be less than the total number of pins (signal terminals) on the IC device under test. This is typically the case where there are groups of pins on the device under test with commonality in terms of timing, so that the number of reference blocks in the set may be limited to only the number of pins in each group. The same set of blocks is then used to calibrate each group of pins on the DUT. One example of this situation is the well known source synchronous bus where there may be many pins on the device under test but for timing purposes they are subdivided into multiple groups of, for instance, 8 pins each, each group with a single associated clock signal. In this case the entire device under test may be subject to calibration using a single set of reference blocks having a number no greater than the number of pins in each group. Hence while the entire device under test may have, for instance, 720 input/output pins. If they are subdivided into 80 groups of 9 pins each, then a set of 9 reference blocks may be sufficient for calibration of the tester apparatus. In other words the reference block technique is useful for large pin count devices that are known by the person doing the testing to have smaller input/output bus groups with tight internal calibration requirements. The above example is a source synchronous bus. Other examples include a source synchronous low voltage differential signaling differential bus. In the case of the low voltage differential signal bus it has been found advantageous to use differential jumper traces on the reference blocks. That is, two jumper traces are provided on each reference block.
Also, another differential type calibration measures timing skew between a true and bar (high and low) output signal from the device under test for a differential (two signal) bus. In this case a set of only two reference blocks is used for the true and bar signal channels.
Also it has been found that various improvements to the reference block to optimize their construction, as disclosed herein.